Nowadays, trench-type MOSFET devices are broadly used as power witches in electronic appliance. The difference between the trench-type MOSFET device and the traditional MOSFET device is that the gate structure of the former is formed in a trench to minimize the area of the MOSFET device, thereby enhancing the density of the MOSFET device and reducing the on-resistance. However, thinning the gate oxide layer to enhance the current drive renders the gate oxide layer more easily affected by the punch-through effect.
Conventional technologies to configure and manufacture high voltage semiconductor power devices are still confronted with difficulties and limitations to further improve the performances due to different tradeoffs. In the vertical semiconductor power devices such as trench-type MOSFET device, there is a tradeoff between the drain to source resistance, i.e., on-state resistance, commonly represented by Rds A (i.e., RdsX Active Area) as a performance characteristic, and the breakdown voltage sustainable of the power device.
Several device configurations have been explored in order to resolve the difficulties and limitations caused by these performance tradeoffs. It is also known that a thick bottom oxide is desirable at the bottom of the trench in order to avoid gate oxide damage during breakdown process. Also, having a thick bottom oxide lowers the gate to drain capacitance. In this approach, a silicon dioxide layer is grown on the exposed silicon at the bottom of the trench. This growth is typically performed using thermal oxidation. However, a drawback of such a technique is that thermal oxidation increases the thermal budget required in the process.
Conventional shielded gate trench (SGT) MOSFET structure also lower reversed transfer capacitance Crss, which equals to the MOSFET gate-to-drain capacitance Cgd. Shielded gate trench MOSFETs are preferred for certain applications over conventional MOSFETs and conventional trench MOSFETs because they provide several advantageous characteristics. Shielded gate trench MOSFETs exhibit reduced gate-to-drain capacitance Cgd, reduced on-resistance RDSon, and increased breakdown voltage of the transistor. For conventional trench MOSFETs, the placement of many trenches in a channel, while decreasing the on-resistance, also increases the overall gate-to-drain capacitance Cgd. Introducing a shielded gate trench MOSFET structure remedies this issue by shielding the gate from the electric field in the drift region with a shield electrode tied to the source potential, thereby substantially reducing the gate-to-drain capacitance. The shielded gate trench MOSFET structure also provides the added benefit of a higher majority carrier concentration in the drift region that improves the device's breakdown voltage and hence lower on-resistance. However, the SGT MOSFET structure presents challenges in forming the dielectric isolation between the shield electrode and gate electrode, unclamped inductive switching (UIS) challenges, and thick shield oxide requirement to optimize breakdown voltage.
Another conventional technique to improve the breakdown voltage and lower the gate to drain capacitance around the trench bottom is forming thick bottom oxide in the trench gate and floating P-dopant islands under the trench gate to improve the electrical field shape. The charge compensation of the P-dopant in the floating islands enables the increasing the N-epitaxial doping concentration, thus reduce the RdsA. In addition, the thick bottom oxide in the trench gate lowers the gate to drain coupling, thus lower the gate to drain charge Qgd. The device further has the advantage to support a higher breakdown voltage on both the top epitaxial layer and the lower layer near the floating islands. However, the presence of floating P region causes higher dynamic on resistance during switching. In addition, high density Trench MOSFET requires self align contact which is a challenging process. Furthermore, even use of a self aligned contact structure limits the cell pitch around 0.8-0.85 μm.
U.S. Pat. No. 5,168,331 to Hamza Yilmaz discloses a metal-oxide-semiconductor field effect transistor (MOSFET) constructed in a trench or groove configuration provided with protection against voltage breakdown by the formation of a shield region adjacent to the insulating layer which borders the gate of the transistor. The shield region is either more lightly doped than, or has a conductivity opposite to, that of the region in which it is formed, normally the drift or drain region, and it is formed adjacent to a corner on the boundary between the insulating layer and the drift or drain region, where voltage breakdown is most likely to occur.
U.S. Pat. No. 7,265,415 to Shenoy et al. discloses a trench MOS-gated transistor that includes a first region of a first conductivity type forming a P-N junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.
U.S. Pat. No. 6,359,306 to Hideaki Ninomiya discloses a trench-MOS gate structure device that includes a first conductivity-type base layer; a second conductivity-type base layer formed on the first conductivity-type layer; a first conductivity-type source layer formed on the second conductivity-type base layer; a plurality of first trenches parallel to each other and penetrating through the first conductivity-type source layer and the second conductivity-type base layer and ending in the first conductivity-type base layer. One gate electrode is formed in each trench. A plurality of second trenches penetrate through the first conductivity-type source layer and end in the second conductivity-type base layer with a main electrode formed in each trench. Portions of the second trenches and portions of the first conductivity-type source layer are alternatively arranged in regions between the first trenches. This trench-MOS gate structure device will enable high packing density thus low specific on resistance (specific on resistance=Die Area times on resistance of the die), however this structure will be extremely fragile as soon as device goes into avalanche breakdown. In addition, built-in parasitic NPN Bipolar Junction Transistor (BJT) will be triggered to turn on locally showing a negative resistance. This effect is sometimes referred to as the Bipolar transistor snap back phenomenon. The parasitic NPN BJT is most likely triggered first in a smaller area of the chip causing hugging of all the current to the smaller area thus destruction of the device by excessive localized heating.
It is within this context that embodiments of the present invention arise.